1. Field of the Invention
The present invention relates to integrated circuit devices, particularly to the field of memory devices.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. One type of memory is Dynamic Random Access Memory (DRAM). DRAMs typically incorporate capacitor and transistor type memory cells. The memory cells temporarily store data based on the charged state of the capacitor structure.
DRAM circuits are increasingly using faster clock frequencies, which results in increased bandwidth for the user. Currently, DRAMs available on the market are capable of clock frequencies in the range of 100 MHz to 400 MHz. Future developments will rapidly push the frequency to 700 MHz and beyond. Additionally, the use of double data rate (DDR) architecture, which transfers four data bits every two clock cycles at the I/O pins, allows the DRAM to further increase its maximum bandwidth.
However, increasing the clock frequency also introduces several problems in addition to the benefits gained in terms of speed. One such problem is a smaller noise margin. The noise margin is the measure of the extent to which a logic circuit can tolerate noise or unwanted spurious signals. With respect to timing, a smaller noise margin results in a smaller time interval during which the charge state of the capacitor can be accurately determined. As the operating frequencies increase, the rise times and fall times of signal pulses can be as long or even longer than the pulse width, thus decreasing the effective pulse widths of the signal pulses.
Intersymbol interference (ISI) can also become a significant factor in the performance of high frequency DRAM. ISI is the distortion of the signal, which is caused by residual energies on a line due to the past history of inputs that had insufficient time to reach a steady state before the next cycle resulting in shrinking bit valid times. The combination of the smaller noise margin and increased intersymbol interference at higher frequencies can result in a loss of performance.
An example of a problem which contributes to ISI is the failure of a switched signal to reach a reference voltage before being switched again. If the voltage on a signal line does not reach the reference voltage, the signal level may not be sufficiently high (or sufficiently low) to be determined unambiguously each time. If the signal level cannot be correctly determined, data that is to be transferred based on the occurrence of the signal may be transferred incorrectly. In order to assure that the signal is received properly, the bit valid time must be increased (e.g., the amount of time during which the signal level can be determined unambiguously must be increased). One method to increase the bit valid time is to dynamically adjust the voltage of the signal. In this method, the low frequency signals are attenuated, and the high frequency portion of the signal is amplified. However, such regulation of the voltage may require additional power supplies or other additional circuit devices that can increase the cost of DRAMs.
Other methods of remedying the foregoing problems have also been proposed. However, the implementation of systems to control intersymbol interference has substantially increased process costs. Thus, a need exists for a solution that addresses the foregoing problems using available control methods.